This is the summary of the course VLSI CAD Part II: Layout from the University of Illinois at Urbana-Champaign. The author of the course is Rob A. Rutenbar. Here’s the summary of the 1st course in the series. Placement Technology mapping Routing Timing Analysis Technology Mapping — transfroming boolean functions/networks into logic gates. Standard Cell Library — a library which contains «standard cells» — logic gates and small logic elements (XOR, NOR, NAND, flip-flop, adder, etc.) Standard Cell can be Читать дальше …
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